EP 2161745 discloses a stack assembly where semiconductor devices are interspersed and compressed between heatsinks. The semiconductor devices have an “open” construction and are not hermetically sealed in a housing. It is believed that semiconductors devices having an “open” construction will benefit most from being immersed in a dielectric liquid. This is because any spaces or gaps between the various component parts of the semiconductor device will be flooded with the dielectric liquid to provide a suitable dielectric environment. The materials used in the semiconductor device must be chemically, structurally and dielectrically compatible with the dielectric liquid so that neither the semiconductor device nor the dielectric liquid are degraded as a result of their contact. It will be readily appreciated that such a semiconductor device is differentiated from one having a conventional press pack construction with a hermetically sealed housing which allows all regions of the semiconductor body to be surrounded and permeated by a suitable moderately pressurised dielectric gas, e.g. dry nitrogen. The semiconductor device also lacks the copper pole pieces that are associated with conventional press pack semiconductor devices. The copper pole pieces are effectively replaced by the heatsinks. The conventional enclosure parts would normally account for about half of the total cost of the conventional press pack semiconductor device. The lack of conventional enclosure parts in a semiconductor device having an “open” construction therefore provides significant cost benefits.
Each semiconductor device comprises a semiconductor body which is encapsulated within a compliant outer ring. The semiconductor body is sandwiched between cathode and anode plates. The outer ring limits the ingress of pollutants into the semiconductor device whilst in storage or when assembled within the stack assembly and protects the semiconductor device against impact or shock during mechanical handling. An important limitation of the semiconductor devices disclosed in EP 2161745 is that the semiconductor bodies have exactly the same construction is those used in industry standard press pack housed arrangement, i.e. they have no features that would enhance voltage breakdown capability or the ratio of effective current carrying area per total area of the semiconductor body. Nor do they exploit the outer ring that surrounds the semiconductor body to provide any dielectric benefit that is specific to higher voltage or wide bandgap power electronic devices.
Emerging wide bandgap electronic materials, for example diamond and silicon carbide, in conjunction with associated processing and fabrication techniques, will allow power electronic devices to block far greater voltages that are currently possible using silicon. However, current field termination and packaging methods will limit the voltage blocking capability, or at least serious limit the effectiveness of improved power electronic devices that employ these new electronic materials. Any references herein to particular electronic or semiconductor materials will be equally applicable to both power semiconductor and other power electronic devices.
A conventional press pack construction has a hermetically sealed housing which is backfilled with a stable dielectric gas such as dry nitrogen. The dielectric gas fills the space around the semiconductor body and is therefore exposed to a significant electric field as it emerges from the body. It is also necessary for the dielectric gas to be chemically compatible with the materials that are employed in the semiconductor device and this precludes the use of many gasses that would otherwise have beneficial properties. In practice the design of the semiconductor body must include features that diffuse the electric field as it emerges from the body to the point where surface breakdown is improbable, taking into account the relatively low breakdown strength of the dielectric gas. The techniques by which the internal electric field of the semiconductor body may be diffused are well known and may be broadly described as: (a) bevelling, (b) doping profiling, (c) the insertion of field control electrodes, and (d) surface passivation. Techniques (b) and (c) are also known as planar edge termination features. These are further described with reference to x and y axes of the semiconductor device where the x axis is projected radially outwards from the centre of the device and the y axis is projected through the axial thickness of the body.
Bevelling:
Bevelling is a geometric feature where the internal electric field is resolved into x and y axis components as it intercepts a conically ground or etched surface. The flatter the conical surface of the bevel the greater the attenuation of surface electric field. Conversely, the more cylindrical the surface of the bevel the lower the attenuation of the surface electric field. The attenuation follows a simple trigonometric relationship in the ideal case where a constant y axis field is present in the semiconductor body. Simple, compound, moat groove and pulley wheel structures are employed and these may be combined with doping profiling. In practice, the doping profile of the semiconductor device has a great impact on bevel performance characteristics.
Doping Profiling:
The doping (i.e. the process of intentionally introducing dopants or impurities into the semiconductor body to change its electrical properties) of the semiconductor body is inherently profiled in the y axis and is usually profiled in the x axis, the latter causing the electric field to be curved as it exits the semiconductor body. Doping profiling is also commonly known as doping contouring. This method may be extended to produce field control electrodes which may be diffused or otherwise implanted within the semiconductor body.
Field Control Electrodes:
Field control electrodes, e.g. guard rings, are implanted or deposited around the periphery of the semiconductor body in order to modify the electric field distribution in the x axis. These electrodes may be conductive, resistive or semiconducting in construction. A number of such features may be employed and the x axis distribution of the electric field is subject to a corresponding number of discontinuities. The intensity of the discontinuities is dependent upon the resolution of the optical process that is employed in the production of the field control electrodes and the nature of the material within the field control electrodes themselves.
Occasionally a derivative of this field control means is employed wherein a field control plate is located around the periphery of the semiconductor body, the surface of the field control plate being parallel to, and spaced apart from, the surface of the semiconductor body and electrically isolated from the surface of the semiconductor body by an insulation medium upon which the field control plate is typically produced by a metallic deposition process. This method is not normally preferred for high voltage devices as a result of the difficulty in controlling the thickness of the insulation medium upon which the field control plate is deposited and, moreover, as a result of electric field concentration resulting from the stepped nature of the field control plate.
Surface Passivation:
Whatever combination of the above techniques is employed, it is generally a requirement that the surface of the semiconductor body outside the metallised contact area is passivated by growing or depositing a dielectric coating upon the otherwise exposed semiconductor structure. The passivation performs two functions: it renders the semiconductor materials substantially insensitive to external sources of ionic pollutants, and it allows the electric field to be further diffused as it exits the semiconductor materials within the semiconductor body according to well known resistive and dielectric principles.
An example of a moat groove bevel, a conical bevel and a pulley wheel bevel are shown in FIGS. 1, 2 and 3, respectively. In each case a semiconductor device includes a semiconductor body 2 with contact metallisation 4, 6 and some form of passivation 8
The ideal form of resolving the internal electric field of the semiconductor body 2 is shown in FIG. 2 where a voltage component Vy within the y axis electric field within the semiconductor body intercepts a bevel surface 10 to give a voltage component Vx aligned with the x axis and which is impressed upon the bevel surface. In this case, the bevel surface voltage gradient is similar to that of Vx in the x axis because the bevel is nearly flat. In the conical bevel shown in FIG. 2 the electric field is also slightly further diffused by the passivation (which is represented by the cross-hatched regions 8) and the associated voltage component at the external surface of the passivation Vp is slightly lower than Vx. In some cases, the passivation 8 may be designed to diffuse the electric field more than in the example shown in FIG. 2 but significant space is occupied by passivation as a result of the limitation of the surface breakdown voltage gradient of the passivation surface in a dry dielectric gas.
The practical limitation of such passivation when used in silicon power semiconductor devices is not evident from FIGS. 1 to 3 because they have not been drawn to scale for reasons of clarity, but the skilled person will be aware that in practical implementation of the pulley wheel bevel shown in FIG. 3 where the semiconductor device has a 6 kV blocking voltage rating, for example, then the axial (or y axis) thickness of the passivation ring 8 will typically be in the region of 5-8 times the axial thickness of the semiconductor body 2 that it surrounds. It will also be noted that the radial thickness of the passivation ring 8 will typically be in the region of 6-10 times the axial (or y axis) thickness of the semiconductor body 2. FIGS. 1 to 3 show passivation rings 8 whose y/x aspect ratio is greater than in reality as a result of having exaggerated the thickness of the semiconductor body 2 in order to make the bevel 10 and corresponding voltage Vy of FIG. 2 legible. When shown to a correct scale, the thickness of the semiconductor body 2 would be a factor of about ten times smaller whereas the axial and radial projections of the passivation rings 8 beyond the surfaces of the semiconductor body would be approximately correct. Also for reasons of clarity the depth of the pulley wheel groove shown in FIG. 3 is approximately correct in relation to the thickness of the semiconductor body 2. The principal advantage that is cited for the example of the pulley wheel bevel that is shown in FIG. 3 is that the contact metallisation areas 4, 6 may closely approach the inside diameter of the passivation ring 8 because the majority of the electric field exits the passivation ring from its outer cylindrical surface, thereby maximising effective current carrying area. Nevertheless, significant housing space is still occupied by the passivation ring 8 and the surrounding gas space. The pulley wheel bevel structure is not applicable to wide bandgap devices because passivation materials that are suitable for use at the limiting electric field strength of the semiconductor or other power electronic devices do not exist, nor are they likely to exist, nor could an effective interface be developed between passivation and electronic materials. A very high performance semiconductor device could be made using a thin wafer of diamond and a pulley wheel bevel passivation material would not be viable unless its breakdown strength was far in excess of that of diamond. It therefore follows that planar edge termination methods are preferred in projected high voltage and wide bandgap devices.
FIG. 4 shows a common planar edge termination technique wherein a number of concentric guard rings 12 or field control electrodes effectively locally short out the x axis component of the electric field as it emerges from the semiconductor body 2. When fine guard ring structures are employed, the thickness requirement for the associated passivation 8 is minimised. It will be readily appreciated that the passivation 8 effectively provides an averaging function for the discontinuous nature of field diffusion provided by multiple guard rings 12. Such guard rings 12 are applied to only one face of the semiconductor body 2, the contact metallisation 6 on the other face of the semiconductor body being extended radially outwards to the same extent as the outermost guard ring.
All of these field diffusion techniques inherently require a proportion of the surface of the semiconductor body 2 to be occupied by geometric features that are outside the effective current carrying area of the semiconductor body, i.e., outside its electrical contact metallisation 4. It follows that the greater the voltage withstand rating of a semiconductor device, the lower the effective current carrying area becomes as a proportion of total area of the semiconductor body 2 and this is a serious impediment to wide bandgap devices that employ present day field control methods.
It is conventional practice to incorporate shedding on the insulation surface of a press pack housing in order to minimise the risk of surface breakdown at its interface with the surrounding air environment. Even when shedding includes long creepage distances and reasonable measures are taken to maintain the surrounding air in a clean, dry state, the risk of surface breakdown is significant. In practice the shedding features are sufficient to allow surface breakdown or tracking to be avoided under ideal conditions, but maintenance deficiencies and abnormal operating conditions that result in surface particulate deposits or condensation being on or even bridging the shedding may lead to breakdown. The space that is occupied by such air insulation systems must have a significant impact upon total equipment power density if this risk is to be mitigated.
It is also known for passivated die-type semiconductor devices with the above moat groove type bevel and ring type field control electrodes to be used in power modules wherein the die is mounted on an insulation material substrate by any suitable means, connected to internal busbars by any suitable means and is encapsulated in a dielectric gel before the power module is permanently sealed within a plastic housing. Moreover, it is known that the dielectric gel supplements the passivation in order to allow the complete power module to attain a breakdown voltage capability that is at least equal to that of the internal capability of the die. Despite the benefit provided by the dielectric gel, such gels have limited ability to enhance breakdown voltage beyond 6.5 kV, even when a precisely controlled vacuum impregnation process is employed. For example, FIG. 5 shows an IGBT die structure having a blocking voltage rating of 3 kV and above. A significant proportion of die area 20 is occupied by passivated guard rings 22 and a sophisticated vacuum impregnation process is required in order for the dielectric gel 24 to provide effective voltage breakdown protection. Gel insulation systems have progressively less insulation performance, and more particularly partial discharge inception performance, as device blocking voltage rating is increased beyond say 4.5 kV. The effective current carrying area of 6.5 kV IGBT die is seriously compromised by gel insulation system performance limitations.
As semiconductor or other power electronic device body internal voltage breakdown capability continues to increase, the requirement to control electric field strength will become increasingly important and present day insulation and packaging systems will seriously compromise the potential benefits that are offered by wide bandgap electronic materials. This issue will be further exacerbated as newly introduced wide bandgap electronic materials and processing techniques permit thinner semiconductor bodies to be employed, thereby tending to concentrate the un-mitigated electric field at the edges of the contact metallisation regions. In practice, the thinner a semiconductor body is, the less effective bevelling is and the above-described planar edge termination methods must be employed in high performance wide bandgap devices. Passivation is an almost mandatory requirement and is able to supplement any form of edge termination for field diffusion purposes. Voltage breakdown and edge termination are very complex subjects and a detailed description can be found in Chapter 3 of “Fundamentals of Power Semiconductor Devices”, B. Jayant Baliga, ISBN-10: 0387473130, ISBN-13: 978-0387473130.